1. Field of the Invention
The present invention relates, generally, to memory management, and in particular embodiments, to the use of abstracted signature tags for the efficient memory management of data elements stored in flash memories.
2. Description of Related Art
A generalized representation of an exemplary computing system is illustrated in FIG. 1. A computer or server identified generally herein as a host 100 is connected to a host bus 102 (e.g. a PCI-X bus). The host 100 typically includes one or more host processors 104, cache 106, and main memory 108. Also attached to the host bus 102 is at least one host (e.g. a host bus adapter (HBA), an I/O controller, or the like), configured by its firmware as an interface to the host 100 and identified generally herein as a host interface port 110. The host 100 and the host interface ports 110 may all reside within the same chassis or on the same circuit board.
The host interface port 110 may include a controller chip 112 incorporating many of the functions performed by the host interface port 110, and flash memory 114. The controller chip 112 may be employed in a HBA for transferring data between devices connected to the host bus 102 and one or more storage devices in one or more storage area networks (SANs) 116 (i.e. a link). In the example system illustrated in FIG. 1, the controller chip 112 may support multiple channels or ports and FC (Fibre Channel), SAS (Serial Attached SCSI) and SATA (Serial ATA) protocols. Each channel on the controller chip 112 comprises a serializer/deserializer (SerDes) 118 and a FC/SAS/SATA protocol core engine (FSENG) 120 coupled to the SerDes 118. A bus interface unit 122 couples one or many FSENGs 120 to SRAM 124 and to multiple processors 126 via a processor bus 128. Also connected to the processor bus 128 is a universal asynchronous receiver/transmitter (UART) 130, an address translation unit 132, and an interprocessor messaging unit (IMU) 134.
The external flash memory 114 is inexpensive, nonvolatile, and high capacity, but also slow. The flash memory 114 is available throughout the operation of the computing system. When the host interface port 110 is initialized, boot code in the flash memory 114 is first executed, other areas of the flash memory 114 are read to determine how to configure the Bus Interface Unit 122, so that the Host 100 can complete the configuration of the Host bus 102, and the firmware initially stored in external flash memory 114 is copied into the SRAM 124. The processors 126 then execute the firmware stored in the SRAM 124, and also utilize their own cache for storing code and data.
FIG. 2 illustrates an exemplary flash configuration space 200 (e.g. a 128 kByte area) in flash memory for storing parameters, settings, and other configuration data to configure the processors, the FSENGs, the SerDes, the host bus, and the like. Flash memory is utilized to store configuration data because it is nonvolatile. The configuration space 200 is partitioned into N configuration data regions 202 (e.g. 32 regions) of a fixed size (e.g. 4 kBytes) for storing the configuration data. In conventional host interface ports that support one or a few channels and a single protocol, only a few of the N configuration data regions 202 are needed to store the configuration data for the system. Each of the configuration data regions 210 stores configuration data 214 for a particular entity (e.g. a SerDes, a FSENG, a processor, a host bus, or the like), written into the flash memory by the firmware. Each configuration data region 210 also includes a header 204, which contains a region identifier 206 and a data depth indicator 208, which may comprise a bitmap or other data structure that indicates how far into the configuration data region 210 the configuration data 214 has been written. For example, a data depth indicator bitmap 208 may contain bits that are set to zero every time another fixed sized block of updated configuration data 214 is written into the configuration data region 210.
Although configuration data 214 is written into the configuration data regions 202 by the firmware, the writing of configuration data 214 can be initiated by either the firmware or the host. When the writing of configuration data 214 is initiated by the host, a software driver in the host (see FIG. 1) sends a request (containing the region identifier 206 and the configuration data 214) to the firmware to write the configuration data 214 into one of the N configuration data regions 202.
The flash memory is erasable in discrete sectors or flash erase units. In other words, the flash memory must be erased in blocks. The configuration space 200 is equivalent to one or more complete flash erase units, and therefore must be erased all at once. Each configuration data region 210 is large enough to store one or more outdated versions of configuration data 216 and a current version of the configuration data 214. When updating the configuration data region 210 with current configuration data 214, it is generally preferable to keep the outdated configuration data 216 rather than erase it, because the alternative is to erase not only the outdated configuration data 216 for that configuration region 210, but all N configuration data regions 202 in the flash configuration space 200, due to the limitation that the flash must be erased in blocks that contain multiple configuration regions 210.
When an update to the configuration data is needed, the firmware executes an update configuration command. To perform the update configuration command, the firmware first locates the proper configuration data region 210. Next, the data depth 208 is used in conjunction with the known fixed size of each block of configuration data for that particular configuration data region 210 to determined the next available location in the configuration data region 210. The updated configuration data 214 is written into the next available location, and the data depth 208 is updated.
A similar procedure is used when the firmware wants to simply read configuration data from the flash configuration space 200. To read particular configuration data, the proper configuration data region 210 is located, the data depth is used 208 in conjunction with the known fixed size of each block of configuration data for that particular configuration data region 210 to determined the location of the current configuration data 214 in the configuration data region 210, and the current configuration data 214 is read from the configuration data region 210 and stored into SRAM in the host interface port for subsequent use in configuring entities within the computing system.
Referring again to the updating of configuration data, eventually, after multiple updates to the same configuration data region 210, the data depth 208 will indicate that the configuration data region 210 is full or nearly full. When this occurs, and another update to the configuration data for that configuration data region 210 is required, a housekeeping procedure must first be performed.
The housekeeping procedure is initiated when an update to a configuration region 210 is requested and no space is available in that region. To perform the housekeeping procedure, all of the data in the flash configuration space 200 is initially saved off to another region of memory. The flash configuration space 200 is then erased, and then only the current, updated configuration data for the various configuration data regions 202 is written back into the flash configuration space 200. By so doing, the obsolete configuration data is eliminated from the configuration data regions 202, and further updates are again possible. However, the erasing of the flash configuration space 200 is time-consuming and can be inefficient, especially if one set of configuration data stored in one particular configuration data region 210 is constantly updated. In that case, although one configuration data region 210 may be getting filled up, many of the other configuration data regions 202 are empty or nearly empty, and yet all configuration data regions 202 within a flash erase unit must be saved off, erased, and re-written.
As described above, in conventional host interface ports that support one or a few channels and a single protocol, the N configuration data regions 202 are generally sufficient to store the configuration data for the system. However, for host interface ports that have multiple channels (and therefore multiple FSENGs and multiple SerDes) and that handle multiple protocols (e.g. FC, SAS, and SATA), many more configuration data regions 210 may be needed to store all of the configuration data. To accommodate the increased number of configuration data regions within the same flash configuration space 200, each configuration data region 210 would become so small (e.g. 32 Bytes) that the regions would quickly fill up, requiring many housekeeping procedures and time-consuming erasures of the flash configuration space 200.
Therefore, a need exists to rearrange the flash configuration space in an efficient manner that minimizes the frequency of erasing the flash configuration space and enables the storing of configuration data for multi-channel, multi-protocol host interface ports.